This invention relates in general to designing integrated circuit processors which incorporate diagnostic characteristics and in particular to generating element layouts within an operational block of an integrated circuit for improved diagnostic operations.
Testability (the ability to perform diagnostic operations) is of high and growing importance in the field of integrated circuit (IC) design and production. Testability generally affects the design and manufacturing costs of ICs as well as the reliability of the final product supplied to customers. Various prior art approaches to incorporating diagnostic ability or testability in IC design have generally been limited by IC performance. Scan chains have generally been used to present a digital xe2x80x9csnapshotxe2x80x9d or status of a chip at a particular moment. It is generally desirable when conducting debugging operations to provide such status information to external equipment in order to evaluate the performance, functionality, and/or electrical robustness of an integrated circuit or portion thereof.
Integrated circuits are commonly designed employing xe2x80x9cplace and routexe2x80x9d build tools in order to compose a chip prior to actual fabrication of the chip. Such place and route tools may involve either manual or automatic placement of functional elements, such as state elements and scan elements, within a functional region of an IC. Another variable in the design of testability in ICs is the design choice of employing either single clocks or non-overlapping clocks for scanning data out of an IC for diagnostic operations. The selection of manual or automated design as well as the selection of either single or non-overlapping clocks in the prior art each have their advantages and disadvantages which are discussed below.
Herein, a xe2x80x9crace conditionxe2x80x9d is a condition wherein the relative placement of certain elements may cause the outcome of a logical operation to change and present an erroneous result based upon the rate of travel of various signal through the IC. Generally, careful design of the layout of elements in an IC may operate to prevent race conditions. An uncured race condition may operate to render an IC inoperative because of the attendant unreliability of data within such an IC.
Generally, employing manual operation permits the designer to acquire a large measure of control over the placement of various elements within the IC. This high level of control generally enables race conditions to be avoided through a careful placement of functional elements within an IC. Where race conditions are avoided through the use of careful manual design, single clocks may be employed scanning data out of the IC for diagnostic purposes. However, manually placing the elements within an IC is generally extremely expensive and time consuming and is generally cost prohibitive once the IC surpasses some reasonable threshold of complexity. Therefore, it is a problem in the art that the benefit of careful manual placement of scan elements within an IC generally imposes an unacceptable cost.
Generally, using automated design tools to place and route the various elements in an IC is far more rapid and less expensive than performing the operation manually. However, using automated design generally presents the prospect of a large number of race conditions among the elements because of the lack of control of element placement and wiring. Generally, non-overlapping clocks may be deployed to address the race conditions created through the use of automated design. However, the use of non-overlapping clocks to coordinate the scanning of data out of an IC for diagnostic purposes generally presents the problems of requiring the implementation of more complex wiring, a greater total quantity of wiring, hotter operation of the IC, greater power consumption by the IC, and slower processing speed of the IC.
In the prior art, control of race conditions and clock skew could be accomplished via the use of balanced clock trees and clock grids. However, the use of balanced clock trees tends to require an inordinate input of Engineering work effort. Moreover, use of a clock grid tends to require excessive power input. Accordingly, the use of balanced clock trees and/or clock grids does not present attractive solutions for the problems of clock skew and race conditions.
Accordingly, it is a problem in the art that the benefit of careful placement of scan elements within an IC arising from manual design generally requires excessive design time and excessive cost.
It is a further problem in the art that the use of automated design tools for the placement of scan elements in an IC generally presents the problem of race conditions which generally requires deployment of non-overlapping clocks.
It is a still further problem in the art that deploying non-overlapping clocks for the purpose of addressing race conditions causes the IC to operate hotter, slower, and to consume more energy than ICs employing single clocks.
The present invention is directed to a system and method which partitions an IC or functional block of an IC into clock regions and locates scan elements within these regions with each such region having a dedicated clock trunk line. Sequences of scan elements within each region may be connected to form scan chains along which scan data may be propagated. A plurality of such scan chains may be daisy chained in sequence so as to provide a single resulting scan chain.
In a preferred embodiment, within each clock trunk line, a scan enable signal is preferably propagated in a direction opposite the direction of propagation of scan information from the various scan elements to thereby prevent the generation of race conditions. Employing the inventive approach, each scan element will preferably transmit data to a downstream scan element (in the direction of scan chain data propagation) before data from an upstream scan element is transmitted into that scan element, thereby avoiding any accidental overwriting of data in the scan element.
Preferably, the one or more clock trunk lines are associated with a single clock, thereby enabling the IC to have a smaller quantity of wiring and reduced wiring complexity in comparison with systems employing non-overlapping clocks. Moreover, an automated design tool is preferably employed to provide initial placement of the various scan elements and to provide subsequent relocation or xe2x80x9csnappingxe2x80x9d of the scan elements to an appropriate clock region, thereby providing the time and cost savings of automated design over manual design.
Herein, the term xe2x80x9cstate elementxe2x80x9d generally refers to an element of an IC capable of storing a state for at least one clock cycle, the term xe2x80x9cscan elementxe2x80x9d generally refers to an element which participates in a diagnostic operation pertaining to the IC by having its state scanned out of the IC to external equipment for diagnostic purposes, and the term xe2x80x9cscan chainxe2x80x9d generally refers to a sequence of devices along which scan data is transmitted.
In a preferred embodiment, a functional clock is employed to control the transmission of functional signals through elements of integrated circuits, such as, for instance, signals pertaining to mathematical operations. Scan clocks are preferably employed to control the transfer of scan data along a chain of scan elements, or scan chain.
In a preferred embodiment, scan elements are provided with an initial timing driven placement within an IC, or functional block within an IC, by an automated design tool. The design tool then preferably relocates, or xe2x80x9csnapsxe2x80x9d the various scan elements to the closest of one or more pre-placed clock lines. Preferably, the above approach minimizes clock skew and clock routing inside the block. The scan chain is then preferably partitioned according to the clock regions associated with the pre-placed clock lines or clock trunk lines.
Accordingly, it is an advantage of a preferred embodiment of the present invention that a scan operation employing a single clock may be combined with automated design while avoiding race conditions, thereby enabling improved cost and time efficiency in the design of an IC.
It is a further advantage of a preferred embodiment of the present invention that partitioned scan chains allow designers to explicitly control the scan routing direction and eliminate race conditions in an integrated circuit.
It is a still further advantage of a preferred embodiment of the present invention that scan chains are partitioned according to clock region in order to minimize the scan routing distance.
It is a still further advantage of a preferred embodiment of the present invention that the use of a partitioned scan chain allows designers to buffer enable signals without modifying the place and route results which generally allows for faster turnaround time in converting a schematic into artwork suitable for fabricating the IC.
It is a still further advantage of a preferred embodiment of the present invention that race conditions and clock skew may be controlled without the inordinate Engineering input required for a balanced clock tree or the excessive power requirements of a clock grid.
It is a still further advantage of a preferred embodiment of the present invention that partitioning according the clock region or xe2x80x9cregioningxe2x80x9d enables wire lengths between various scan elements to be reduced.
It is a still further advantage of a preferred embodiment of the present invention that regioning avoids noise and drive strength issues.
The foregoing has outlined rather broadly the features and technical advantages of the present invention in order that the detailed description of the invention that follows may be better understood. Additional features and advantages of the invention will be described hereinafter which form the subject of the claims of the invention. It should be appreciated by those skilled in the art that the conception and specific embodiment disclosed may be readily utilized as a basis for modifying or designing other structures for carrying out the same purposes of the present invention. It should also be realized by those skilled in the art that such equivalent constructions do not depart from the spirit and scope of the invention as set forth in the appended claims. The novel features which are believed to be characteristic of the invention, both as to its organization and method of operation, together with further objects and advantages will be better understood from the following description when considered in connection with the accompanying figures. It is to be expressly understood, however, that each of the figures is provided for the purpose of illustration and description only and is not intended as a definition of the limits of the present invention.